electronic-lab January 2011

electronic-lab@lists.fedoraproject.org

2 participants
14 discussions

[Fedora-electronic-lab] [Fedora Electronic Lab] #20: package myHDL

by fedora-badges

#20: package myHDL ----------------------+----------------------------------------------------- Reporter: chitlesh | Owner: chitlesh Type: task | Status: new Priority: major | Milestone: Fedora 12 Component: FEL | Version: devel Keywords: | ----------------------+----------------------------------------------------- Upstream was contacted to encourage them to package myHDL for FEL. Upstream responded by saying he will ask his community. -- Ticket URL: <https://fedorahosted.org/fedora-electronic-lab/ticket/20> Fedora Electronic Lab <https://fedorahosted.org/fedora-electronic-lab> Design, Simulate and Program electronics.

12 years, 11 months

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[fedora-electronic-lab] [Fedora Electronic Lab] #91: Package ForSyDe

by fedora-badges

#91: Package ForSyDe -----------------------------------------------------+---------------------- Reporter: shakthimaan | Owner: shakthimaan Type: task | Status: new Priority: major | Milestone: Fedora 13 Component: FEL | Version: devel Keywords: formal method, hardware design, haskell | -----------------------------------------------------+---------------------- Package ForSyDe (Haskell) by Prof. Ingo Sander from kth.se. http://hackage.haskell.org/package/ForSyDe http://www.ict.kth.se/forsyde/ -- Ticket URL: <https://fedorahosted.org/fedora-electronic-lab/ticket/91> Fedora Electronic Lab <https://fedorahosted.org/fedora-electronic-lab> Design, Simulate and Program electronics.

13 years, 2 months

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just started a new package (Pinguino)

by Kévin Raymond

Hi guys, Have you ever heard about Pinguino[1]? It is an Arduino like board based on Microchip PICs. It is aimed to provide easy tools for usb communication. Just to let you know that I have just started to package it (0.9 beta 5). Let me know if someone is already working on it... I plan to speak about it and FEL during the "Solution Linux"[2] forum held in May at Paris. There are around 10,000 visitors in 3 days. [1] http://www.hackinglab.org/pinguino/index_pinguino.html [2] http://fedoraproject.org/wiki/Solutions_Linux_2011 Regards, -- Kévin Raymond (shaiton) GPG-Key: A5BCB3A2

13 years, 3 months

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vasy giving a Segmentation Fault

by Ashwith Rego

Hi, I wrote some verilog code and from this I generated an equivaltent VHDL code using Icarus Verilog's VHDL code generator. vasy didn't take this so I made some changes going by the errors it gave. The last time I tried it, it gave a Segmentation fault. I ran the following commands: iverilog -t vhdl alu8.v -o alu8.vhdl vasy -Vao alu8.vhdl I have attached my verilog code and the code generated by Icarus (with the changes I made). Is there something in the VHDL code that shouldn't be there? Is there a way to get around this or fix it? Thanks -- Ashwith J. Rego ----------------- My Webpage: http://ashwith.wordpress.com/ Find me on LinkedIn at: http://www.linkedin.com/in/ashwith Follow Me on Twitter at: http://twitter.com/Louisda16th

13 years, 4 months

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electronic-lab January 2011